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在高速串行通信速率持续提升的场景下,传统低压差分信号(LVDS)驱动电路会因共模电平偏移与高频传输衰减的共同作用,出现严重的信号抖动问题。为此,基于65nm CMOS工艺设计了一种低抖动LVDS驱动电路。该工艺通过对比分析传统LVDS 驱动器结构,采用性能更优的双电流源驱动架构,并集成了共模反馈电路与预加重电路。共模反馈电路依托带隙基准电路输出的稳定参考电压,可实现对输出共模电平的精准钳位;预加重电路则通过开关逻辑控制加速信号电平翻转,以此补偿传输过程中的高频分量损失,最终达到减小信号抖动的效果。在2Gbps伪随机编码输入、2.5V 电源电压、TT 工艺角、负载电容2pF的条件下进行仿真,结果表明该电路实现了15.46ps的低峰峰值抖动,输出摆幅385mV,功耗6.9Mw/Gbps,与现有同类设计相比,本文电路的峰峰值抖动较多数设计降低61.35%以上,功耗水平略优于其他同类低压差分信号驱动电路,各项指标均满足ANSI/TIA/EIA-644标准要求。
Abstract:In the scenario of continuous increase in high-speed serial communication rate, traditional low-voltage differential signaling (LVDS) driver circuits will suffer from severe signal jitter due to the combined effect of common-mode level offset and high-frequency transmission attenuation. To address this issue, a low-jitter LVDS driver circuit is designed based on the 65 nm CMOS process. By comparatively analyzing the structures of traditional LVDS drivers, this design adopts a dual current-source driving architecture with better performance, and integrates a common-mode feedback circuit and a pre-emphasis circuit. The common-mode feedback circuit relies on the stable reference voltage output by the bandgap reference circuit to achieve precise clamping of the output common-mode level. The pre-emphasis circuit accelerates signal level flipping through switch logic control, so as to compensate for the high-frequency component loss during transmission and ultimately achieve the effect of reducing signal jitter. Simulations are carried out under the conditions of 2 Gbps pseudo-random code input, 2.5 V power supply voltage, TT process corner, and 2 pF load capacitance. The results show that the circuit achieves a low peak-to-peak jitter of 15.46 ps, an output swing of 385 mV, and a power consumption of 6.9 mW/Gbps. Compared with existing similar designs, the peak-to-peak jitter of the proposed circuit is reduced by more than 61.35% compared with most designs, and its power consumption performance is slightly better than other similar LVDS driver circuits. All indicators meet the requirements of the ANSI/TIA/EIA-644 standard.
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基本信息:
中图分类号:TN432
引用信息:
[1]梁蔚,周顺勇,林伟,等.一种基于CMOS工艺的低抖动LVDS驱动电路设计[J].四川轻化工大学学报(自然科学版)().
基金信息:
国家自然科学基金项目(61801319)
2026-10-12
2026-10-12
2026-10-12